Memory, Evolution or Revolution?

Memory
Evolution or Revolution?

JEDEC SDRAM

All DRAM memory that has a synchronous interface is known generically as SDRAM. This includes CDRAM (Cache DRAM), RDRAM (Rambus DRAM), ESDRAM (Enhanced SDRAM) and others, however the type that most often is called SDRAM is, in reality, the JEDEC standard synchronous DRAM.

JEDEC SDRAM not only has a synchronous interface controlled by the system clock, it also includes a dual-bank architecture and burst mode (1-bit, 2-bit, 4-bit, 8-bit and full page). A ‘mode register’ that can be set at power-on and changed during operation controls the burst mode, burst type (sequential or interleave), burst length and CAS latency (1, 2 or 3).

CAS Latency is one of several performance related timings for SDRAM. This measurement is the time it takes to strobe in the Row Address, and to activate the bank. When a burst read cycle is initiated, the addresses are set up and RAS\ and CS\ (chip select) are held low on the next clock cycle (rising edge of CLK), thereby activating the sense amplifiers on the bank. A period of time equal to ^tRCD (RAS\ to CAS\ delay) must pass after which CAS\ and CS\ are held low (again, at the next clock cycle). After the time period for ^tCAC (column access time) has passed the first bit of data is on the output line and can be retrieved (at the next clock cycle). The basic rule is that CAS latency times the clock speed (^tCLK) must be equal or greater than ^tCAC (or CL x ^tCLK >= ^tCAC). This means that the column access time is the limiting factor for CAS Latency.

Early in its development, SDRAM was initially thought to be the fast answer to all bus and memory performance problems, however it quickly became apparent that the performance gain was greatly overshadowed by compatibility problems. The first SDRAM modules contained only two clock lines, and engineers were quick to discover that this was insufficient. This resulted in two different module designs, 2-clock and 4-clock, and you needed to know which your motherboard required. Though the timings were theoretically supposed to be 5-1-1-1 at 66 MHz, most of the original SDRAM would only run at 6-2-2-2 when run in pairs, mostly due to the available chipsets at that time, such as the i430VX and SiS5571, which had trouble with the speed as well as coordinating the accesses occurring between modules. The i430TX chipset and later non-Intel chipsets improved upon this, and the SPD chip (serial presence detect) was added to the JEDEC standard so that chipsets could read the timings from the module. This created even more problems though, as the SPD EEPROM was either not included on many modules, or not being read by the motherboards.

SDRAM chips are rated in MHz, rather than nanoseconds (ns) so that there is a common denominator between the bus speed and the chip speed. This speed is determined by dividing 1 second (1 billion ns) by the output speed of the chip. For example a 67 MHz SDRAM chip is rated as 15ns. Note that this nanosecond rating is not measuring the same timing as an asynchronous DRAM chip. Remember from above, internally all DRAM operates in a very similar manner, and most performance gains are achieved by ‘hiding’ the internal operations in various ways.

The original SDRAM modules either used 83 MHz chips (12ns) or 100 MHz chips (10ns), however these were only rated for 66 MHz bus operation. Due to some of the delays introduced when dealing with the various synchronization of signals, the 100 MHz chips will produce a module that operates reliably at about 75 MHz to 83 MHz in many cases. These SDRAM modules were referred to as PC66, to differentiate them from those conforming to Intel’s PC100 specification.

PC100 SDRAM

When Intel began the implementation of its 100 MHz system bus speed, it was understood that most of the SDRAM modules currently available would not operate properly above 83 MHz. In order to avoid some of the problems that had been experienced with EDO and PC66 SDRAM, Intel introduced the PC100 specification in 1998 as a guideline to manufacturers for building modules that would function properly on their upcoming i440BX chipset. This guideline would enable memory makers to create modules that would accommodate both a 66 MHz, as well as a 100 MHz, bus. Along with the PC100 specification, Intel created additional guidelines for trace lengths, trace widths and spacing, number of PCB (printed circuit board) layers, EEPROM programming specs, etc.

Although it doesn’t occur nearly as much today as it did then, at the time the specification was created, there was considerable confusion at to what a “true” PC100 module actually consisted of. Even though the specification has been available for quite some time now, there are still quite a few PC100 modules being advertised and sold as PC100 compliant today that in fact do not meet this specification and do not operate reliably at 100 MHz. In order for any PC100 module to be compliant with the Intel specification, it must use an SDRAM chip that meet a minimum specification of 8ns with internal frequencies running at 125MHz. You can read more about PC100 compliance here. While the chip speed rating is used most often to determine the overall performance of the chip, a number of other timings are very important. ^tRCD (RAS to CAS Delay), ^tRP (RAS precharge time) and CAS Latency all play a role in determining what the fastest bus speed the module will operate on to achieve a 4-1-1-1 timing.

The biggest overall boost that PC100 SDRAM provides is on a 100MHz (or faster) system bus on a late production Socket 7 motherboard system. On average, the performance increase is between 10% and 15%. This is because the L2 cache is running at or near the system bus speed. Pentium II systems will not see as big a boost, because the L2 cache is running at half the processor speed. The exception to all of this though is the cache-less or reduced cache Celeron chips. Obviously, we have excluded the Pentium III and Zeon processors here as we do not consider them in the same processor and bus speed group.

PC133 SDRAM

Most 133 MHz SDRAM chips are actually designed to run as fast as 150 MHz and are often referred to as “-7.5” (7.5 nanosecond). You can identify the chips by reading “-7” in the last of the digits on the chip part numbering found on most PC133 memory modules. The “-7” refers to the minimum operating clock cycle of the device. You can read more about correctly identifying PC 133 modules here.

When Intel introduced the PC100 SDRAM specification in 1998, a list of standards were assembled that needed to be addressed and complied with by both the semiconductor chip and the actual module manufacturers in order for the specification to be uniform. This same specification process followed for PC133.

The current PC133 JEDEC Standard includes the following:

• Minimum and maximum trace lengths for all signals on the module.
• Precise specifications for trace width and spacing.
• Detailed specifications for the distances between each circuit board layer.
• Only 6 layer PCB’s with unbroken power and ground planes to be used.
• Well balanced clock trace lengths, as well as routing, loading, and termination requirements.
• Series termination resistors on all data lines.
• Detailed SDRAM component specifications.
• Detailed EEPROM SPD programming specifications.
• Special Label/Marking Requirements.
• Electro Magnetic Interference (EMI) Suppression.
• Gold plated printed circuit boards.

The PC 133 specification, derived from the collaborative effort of JEDEC and the Intel Corporation, delves deeply into each of the points listed above and dictates what each chip and module manufacturer must do in order to meet the standard. Ideally this should work, however as with many things today, there are scam artists who attempt to re-mark PC 100 modules as PC 133 (forgeries). There are also some unscrupulous manufacturers and black marketers who attempt to sell modules alleged to be PC 100 compliant, when in fact they are modules that should have been sold originally as PC 66. Remember this, to be a JEDEC qualified PC 100 module, it should operate flawlessly at 125 MHz. Likewise, a PC 133 compliant module should run flawlessly at 150 MHz.

Again, under this newly created standard, all SDRAM memory modules, whether PC 100 or PC 133, should be created equal and there shouldn’t be any variation between any two modules made by different companies. This is good in theory, but in the real world, you will find that SDRAM modules with identical SDRAM chips, can reach entirely different frequencies simply because of differences in the manufacturing process of the PCB and the trace layouts on the boards. Therefore, if you plan on adding memory, make sure that the memory you add is identical to that already in your computer. As an example, if your computer has genuine PC100 or PC133 memory let’s say from Micron/Crucial or Samsung, then purchase the additional memory from a source that can match what you have. If your upgrading, then purchase as much of the new memory as you can afford.